1. Field of the Invention
The present invention relates to a method of forming a MOS transistor on a substrate of a semiconductor wafer, and more particularly, to a method of enhancing the electrical performance of a MOS transistor.
2. Description of the Prior Art
With the progressive development of very large scale integration (VLSI) circuits, metal-oxide semiconductor (MOS) transistors that consume less power and that can be highly integrated are widely used in the semiconductor and electronics industries. A MOS transistor typically comprises a MOS capacitor, and two doped regions which are complementary to the substrate, called a source and a drain. When a proper voltage is applied, MOS transistors can be used as a kind of switch to control the flow of electricity through a device. As the development of integrated circuits grows ever more complex and precise, controlling the manufacturing process of MOS transistors becomes an increasingly important issue.
Please refer to FIG. 1. FIG. 1 is a cross-sectional view of a prior art MOS transistor 20. In the following description, an n-type MOS transistor is considered. For the prior art method of forming the MOS transistor 20, p-type dopants are used to dope a substrate of a semiconductor wafer 10. A thermal process is performed to drive the dopants into the substrate so as to form a p-well 12. A thermal oxidation process and a thin film deposition process are then performed on the semiconductor wafer 10 to form a silicon dioxide layer and a doped polysilicon layer.
A photoresist layer (not shown in the figure) is coated onto the surface of the semiconductor wafer 10, and a lithographic process is performed on the photoresist layer to define the pattern of a gate 26. Then a dry etching process is performed to form the gate 26, which comprises a gate oxide layer 22 and a gate electrode 24. The photoresist layer is then stripped. An ion implantation process is performed to form low doping drains (LDD) 14 adjacent to the two sides of the gate 26 of the MOS transistor 20. A chemical vapor deposition (CVD) process is then performed to deposit a silicon nitride layer, and an anisotropic etching process is performed to remove the silicon nitride layer down to the surface of the p-well 12 so as to form a spacer 28 on each lateral side of the gate 26. Using the gate 26 and the spacers 28 as hard masks, an ion implantation process is performed to dope n-type dopants into the p-well 12 so as to form a source 16 and a drain 18 of the MOS transistor 20.
Please refer to FIG. 2 and FIG. 3. FIG. 2 is a diagram depicting the doping distribution in the MOS transistor along the line 2-2xe2x80x2 of FIG. 1. FIG. 3 is a diagram depicting the doping distribution in the MOS transistor along the line 3-3xe2x80x2 of FIG. 1. As shown in FIG. 2, the diagram illustrates the dopant concentration versus depth. Experimental results have shown that the channel doping distribution curve 27 of the MOS transistor 20 is relatively uniform with the rest of the p-well 12, and is higher than desired. This high, uniform doping distribution results in reduced mobility of electrons and holes, and may cause short channel effects (SCE). As shown in the doping distribution curve 29 of FIG. 3, the doping concentration is typically large in both the source 16 and the drain 18. Because the doping concentration at the interface of the source 16 and the p-well 12, or the drain 18 and the p-well 12, is much lower than other source or drain regions, a higher junction capacitance (Cj) may appear at the interface, affecting the electrical performance of the MOS transistor 20.
It is therefore a primary objective of the present invention to provide a method of forming a MOS transistor on a substrate of a semiconductor wafer so as to solve the above mentioned problems.
In a preferred embodiment, the present invention provides a method of forming a Metal Oxide Semiconductor (MOS) transistor on a substrate of a semiconductor wafer. A gate of the MOS transistor is formed on the substrate. A source and a drain of the MOS transistor are then formed in the substrate. An ion implantation process is performed to form a first doped region, a second doped region and a third doped region. The first doped region is positioned under the gate and overlaps with the channel of the MOS transistor. The second doped region is positioned in a predetermined portion of the substrate under the source, and the third doped region is positioned in a predetermined portion of the substrate under the drain. The first doped region, the second doped region, the third doped region, the source, and the drain are all of the same type of semiconductor.
It is an advantage of the present invention that an ion implantation process is performed to form doped regions under the gate, the source and the drain. The doped regions are the same type of semiconductor as the source and the drain, but the doping dosage is lower. This method is used to form a Super Steep Retrograde (SSR) channel doping distribution in the MOS transistor, and is used to reduce the junction capacitance (Cj) at the interface of the source and the well, and at the drain and the well.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.